A pipelined speculative SIMD architecture for SOM ANN

IEEE International Conference on Neural Networks - Conference Proceedings

Volumn 2, Issue , 1997, Pages 985-990

  Hammami, O ^a   Suzuki, D ^a  

^a UNIVERSITY OF AIZU   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTEXT-BASED; HARDWARE IMPLEMENTATIONS; IDLE TIME; SIMD ARCHITECTURE; SYNCHRONOUS DESIGNS; TEMPORAL PARALLELISM;

HARDWARE; NEURAL NETWORKS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; LEARNING ALGORITHMS; PIPELINE PROCESSING SYSTEMS; ROBOTIC ARMS;

ARCHITECTURE; NEURAL NETWORKS;

SELF ORGANIZING MAP ARTIFICIAL NEURAL NETWORKS (SOM ANN);

EID: 0030651572     PISSN: 10987576     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICNN.1997.616160     Document Type: Conference Paper

References (15)

1. K.Siu,V.Roychowdhury and T.Kailath "Discrete Neural Computation, a Theoretical Foundation ", Prentice Hall Information and System Science Series, 1995.
2. T.Kohonen "Self Organizing Maps" Springer Series in Information Sciences, Vol. 30, Springer DEU, 1995.
3. B.J.Sheu and J.Choi "Neural Information Processing and VLSI", Kluwer Academic Publishers, 1995.
4. P.Ienne,T.Cornu and G.Kuhn "Special Purpose Digital Hardware for Neural Networks: An Architectural Survey", Journal of VLSI Signal Processing Systems 13,5-25,1996.
5. J.Hennessy and D.Patterson," Computer Architecture-A Quantitative Approach".2nd Ed., Morgan Kaufman Pub.1996.
6. J.D.Allen and D.E.Schimmel "Issues in the Design of High Performance SIMD Architectures",IEEE Trans, on PADS,pp.818-829, Vol.7, No.8,August 1996.
7. M.K.Milligan and H.G.Cragon " Processor Im plementations Using Queues", IEEE Micro,pp.58-65, Aug.1995.
8. B.Pino,F.J.Pelayo and A.Prieto " A Digital Implementation of Self Organizing Maps"in Proc. of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, pp.260-267, Turin, Italy, Sept.26-28, 1994.
9. S.Rueping,K.Goser and U.Rueckert "A Chip for Selforganizing feature maps" in Proc. of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, pp.26-33, Turin, Italy, Sept.26-28, 1994.
10. B.Brio and J.Alberto/'Hardware Oriented Models for VLSI Implementation of SOM ",in Proc. of IWANN'95,pp.712-719.June 1995,LNCS 930, Springer.
11. P.Moerland and E.Fiesler" Hardware Friendly Learning Algorithms for Neural Networks: An Overview" in Proc. of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems,pp.117-124, Lau-sanne,Switzerland, Feb.12-14, 1996.
12. S.Ruping and U.Ruckert" A Scalable Processor Array forSelf Organizing Maps"in Proc. of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems,pp.285-291, Lausanne,Switzerland, Feb.12-14, 1996.
13. T.Serrano and B.Barranco " A Real Time Clustering Microchip Neural engine" IEEE Trans, on VLSI systems,pp.l95-209, Vol.4,No.2,June 1996.
14. T.Hamalainen et al.," Neuron Parallel Implementation of MLP on Tree Shape Neurocom-puter ", in Proc. of the World Congress on Neural Networks,pp.1351-1354,San Diego, CA,Sept 15-18,1996.
15. Y.Kondo et al "A 1.2 Gflops Neural Network Chip for High Speed Neural Network Servers" IEEE Journal of Solid State Circuits, Vol.31, No.6,pp. 860-864, June 1996.