25 to 300°C ultra-low-power voltage reference compatible with standard SOI CMOS process

Electronics Letters

Volumn 38, Issue 19, 2002, Pages 1103-1104

  Adriaensen, S ^a   Dessard, V ^b   Flandre, D ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b CISSOID SA   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

ULTRA-LOW-POWER VOLTAGE REFERENCES;

VOLTAGE STABILIZING CIRCUITS;

EID: 0037068703     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020768     Document Type: Article

References (5)

1. ADRIAENSEN, S., DESSARD, V., and FLANDRE, D.: 'A bandgap circuit operating up to 300°C using lateral bipolar transistors in thin-film CMOS-SOI technology'. Proceedings of the IEEE 1999 International SOI Conference, Rohnert Park, CA, USA, October 1999.
2. EGGERMONT, J.-P., DESSARD, V., VANDOOREN, A., FLANDRE, D., and COLINGE, J.-P.: 'SOI current and voltage reference sources for applications up to 300°C'. Fourth International High Temperature Conference, Albuquerque, USA, June 1998, pp. 55-59.
3. Silvaco, Atlas v.5.2.0.R., 1998
4. FLANDRE, D., COLINGE, J.P., CHEN, J., DE CEUSTER, D., EGGERMONT, J.P., FERREIRA, L., GENTINNE, B., JESPERS, P.G.A., VIVIANI, A., GILLON, R., RASKIN, J.P., VANDER VORST, A., VANHOENACKER, D., and SILVEIRA, F.: 'Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits', Analog Integr. Circuits Signal Process., 1999, 21, (3), pp. 213-228.
5. Patent Application PCT/EP01/15023.