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Volumn 12, Issue , 2002, Pages 601-606

A multilevel architecture for FPGA based implementation of feed-forward neural network for pattern recognition

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BACKPROPAGATION; FACE RECOGNITION; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE ANALYSIS;

EID: 0036999912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (8)
  • 3
    • 84943242999 scopus 로고
    • Hardware implementation of an artificial neural network
    • Botros, N.M., and Abdul-Aziz, M., 1993, "Hardware implementation of an Artificial Neural Network," In Proc. ICNN, vol.3, pp. 1252-1257.
    • (1993) Proc. ICNN , vol.3 , pp. 1252-1257
    • Botros, N.M.1    Abdul-Aziz, M.2
  • 4
    • 0013411632 scopus 로고    scopus 로고
    • Hardware FPGA implementation of a neural network
    • Cimpu, V.F., 1996, "Hardware FPGA Implementation of a Neural Network," In Proc.Int.Conf. Technical Informatics, vol 2, pp 57-68.
    • (1996) Proc.Int.Conf. Technical Informatics , vol.2 , pp. 57-68
    • Cimpu, V.F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.