An asynchronous cell library for self-timed system designs

IEICE Transactions on Information and Systems

Volumn E80-D, Issue 3, 1997, Pages 296-305

  Pang, Yuk Wah ^a   Sit, Wing Van ^a   Choy, Chiu Sing ^a   Chan, Cheong Fat ^a   Cham, Wai Kuen ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Asynchronous design; Self limed logic; Standard cell; VLSI

Indexed keywords

COMPUTER SIMULATION; COMPUTER SIMULATION LANGUAGES; DELAY CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; PERFORMANCE; TIMING CIRCUITS; VLSI CIRCUITS;

ASYNCHRONOUS CELL LIBRARY; ASYNCHRONOUS DESIGN; GLOBAL CLOCK; MICROPIPELINE TECHNIQUE; MULLER MODEL; SELF TIMED SYSTEM DESIGN; STANDARD CELL LIBRARY;

LOGIC DESIGN;

EID: 0031100826     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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