A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells

IEEE Electron Device Letters

Volumn 23, Issue 7, 2002, Pages 422-424

  Cho, Caleb Yu Sheng ^b   Chen, Ming Jer ^a,b   Lin, Jia Han ^b   Chen, Chiou Feng ^c  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c Actrans System Inc   (United States)

Author keywords

Body effect; Capacitance coupling; Flash memory; Mismatch; MOSFETs; Subthreshold

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC CURRENT MEASUREMENT; ERRORS; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

CAPACITANCE COUPLING COEFFICIENTS; FLASH MEMORY CELLS; GATE VOLATGE SHIFT; PROCESS VARIATION IMMUNITY METHOD; SOURCE TO SUBSTRATE BIAS; SUBTHRESHOLD SWING RATIO; WEAK BODY EFFECT;

FLASH MEMORY;

EID: 0036645829     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.1015226     Document Type: Article

References (8)

1. Analysis of the subthreshold slope and the linear transconductance techniques for the extraction of the capacitance coupling coefficients of floating-gate devices
2. Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells
3. Characterization and modeling of mismatch in MOS transistors for precision analog design
4. Matching properties of MOS transistors
5. Measurement of MOS current mismatch in the weak inversion region
6. Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling
7. A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation
8. Analysis and modeling of floating-gate EEPROM cells