Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 3, 2002, Pages 292-300

  Muhammad, Khurram ^b   Roy, Kaushik ^a,c  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Adaptive computing; Arithmetic; Computing; High performance; Low power design; Number representation; Performance tradeoffs; System level

Indexed keywords

ADAPTIVE COMPUTING; COMPUTATION SHARING VECTOR SHARING; LOW-POWER DESIGN;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DIGITAL ARITHMETIC; MULTIPLYING CIRCUITS; PERFORMANCE; RANDOM ACCESS STORAGE; TABLE LOOKUP;

DIGITAL SIGNAL PROCESSING;

EID: 0036625423     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043332     Document Type: Article

References (16)

1. K. K. Parhi, Digital Signal Processing Systems. New York: Wiley, 1999.
2. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1994.
3. S. Ramaswamy and R. E. Siferd, "CMOS VLSI implementation of a digital logarithmic multiplier," in Proc. IEEE 1996 Nat. Aerospace Electron. Conf. NAECON 1996, Dayton, OH, May 1996, pp. 20-23.
4. H. R. Srinivas and K. K. Parhi, "High-speed VLSI arithmetic processor architectures using hybrid number representation," J. VLSI Signal Processing, vol. 4, no. 2-3, pp. 177-198, May 1992.
5. E. E. Swartzlander, "Computer Arithmetic," IEEE Comput. Soc. Press, 1990.
6. S. E. McQuillan and J. V. McCanny, "A systematic methodology for the design of high performance recursive digital filters," IEEE Trans. Comput., vol. 44, pp 971-982, Aug. 1995.
7. J. K. Jain, L. Song, and K. K. Parhi, "Efficient semisystolic architectures for finite-field arithmetic," IEEE Trans. VLSI Syst., vol. 6, pp. 101-113, Mar. 1998.
8. W. L. Gallagher and E. E. Swartzlander, "High radix booth multipliers using reduced area adder trees," in Twenty-Eighth Asilomar Conf. Signals, Syst., Comput. Piscataway, NJ: IEEE Press, 1994, vol. 1, pp. 545-549.
9. S. M. Sait, A. A. Farooqui, and G. F. Beckhoff, "A novel technique for fast multiplication," in Proc. IEEE 1995 14th Ann. Int. Phoenix Conf. Comput. Commun., 1995, pp. 109-114.
10. C. Martel, V. Oklobdzija, R. Ravi, and P. F. Stelling, "Design strategies for optimal multiplier circuits," in Proc. IEEE 12th Symp. Comput. Arithmetic. Picataway, NJ: IEEE Press, 1995, pp. 42-49.
11. R. B. Staszewski, K. Muhammad, and P. T. Balsara, "A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels," IEEE J. Solid-State Circuits, vol. 35, pp. 1205-1210, Aug. 2000.
12. K. Muhammad and K. Roy, "Switching characteristics of generalized array multiplier architectures and their applications to low power design," in Proc. Int. Conf. Comput. Design (ICCD '99), Oct. 10-13, 1999, pp. 230-235.
13. A. K. Kwentus, H.-T. Hung, and A. N. Wilson, Jr., "An architecture for high-performance/small-area multipliers for use in digital filtering applications," IEEE J. Solid-State Circuits, vol. 29, pp. 117-121, Feb. 1994.
14. K. Muhammad, R. B. Staszewski, and P. T. Balsara, "Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels," IEEE Trans. VLSI Syst., vol. 9, pp. 42-51, Feb. 2001.
15. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, MA: MIT Press, 1990.
16. K. Muhammad and K. Roy, "Algorithmic and architectural techniques for low-power digital signal processing," Ph.D. dissertation, Dept. Elect. Comput. Eng., Purdue University, West Lafayette, May 1999.