Wafer scale integration neural network utilizing completely digital circuits

IJCNN Int Jt Conf Neural Network

Volumn , Issue , 1989, Pages 213-217

  Yasunaga, Moritoshi ^a   Masuda, Noboru ^a   Asai, Mitsuo ^a   Yamada, Minoru ^a   Masaki, Akira ^a   Hirai, Yuzo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS, DIGITAL--TIME SHARING; INTEGRATED CIRCUITS, DIGITAL;

REDUNDANT LEARNING CONTROL; WAFER SCALE INTEGRATION NEURAL NETWORK;

SYSTEMS SCIENCE AND CYBERNETICS;

EID: 0024910802     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)