Layout-based statistical modeling for the prediction of the matching properties of MOS transistors

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 5, 2002, Pages 680-685

  Conti, Massimo ^a   Crippa, Paolo ^a   Orcioni, Simone ^a   Turchetti, Claudio ^a  

^a UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

Mismatch; Partitioned layout; Statistical modeling; Stochastic process

Indexed keywords

CORRELATION METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; PARAMETER ESTIMATION; RANDOM PROCESSES; SEMICONDUCTOR DEVICE MODELS;

AUTOCORRELATION FUNCTION; COMMON CENTROID STRUCTURES; INTERDIGITATED STRUCTURES; MATCHING PROPERTIES; STATISTICAL MISMATCH ANALYSIS;

MOSFET DEVICES;

EID: 0036576882     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.1001958     Document Type: Article

References (10)

1. Matching properties of MOS transistors
2. Applying a submicron mismatch model to pratical IC design
3. Threshold voltage mismatch in short channel MOS transistors
4. Optimizing MOS transistor mismatch
5. Matching of MOS transistors with different styles
6. Mismatch distance term compensation in centroid configurations with nonzero-area devices
7. Parametric yield formulation of MOS IC's affected by mismatch effect
8. Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function