A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process

IEEE Electron Device Letters

Volumn 23, Issue 5, 2002, Pages 237-239

  Wu, Jau Yi ^b   Wang, Hwei Heng ^b   Sze, Po Wen ^c   Wang, Yeong Her ^a,b   Houng, Mau Phon ^b  

^a IEEE

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c KAO YUAN INSTITUTE OF TECHNOLOGY   (Taiwan)

Author keywords

GaAs; Isolation; Liquid phase; Oxidation

Indexed keywords

ANNEALING; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); LOW TEMPERATURE OPERATIONS; MASKS; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; OXIDATION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING GALLIUM ARSENIDE; THERMODYNAMIC STABILITY;

DIFFERENTIAL RESISTANCE; LIQUID PHASE ENHANCED OXIDATION PROCESS; MESA ISOLATION; PLANARIZED SHALLOW TRENCH ISOLATION; SELECTIVE OXIDIZED GATE;

MOSFET DEVICES;

EID: 0036575892     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.998862     Document Type: Letter

References (10)

1. Corner-parasitics-free low-cost trench isolation
2. Platop: A novel planarized trench isolation and field oxide formation using poly-silicon
3. Roles of sidewall oxidation in the devices with shallow trench isolation
4. Isolation implant studies in GaAs
5. Proton isolation of Si δ-doped GaAs
6. Liquid phase chemical-enhanced oxidation for GaAs operated near room temperature
7. Effect of crystal orientation and doping on the activation energy for GaAs oxide growth by liquid phase method
8. Effects of pH values on the kinetics of liquid phase chemical-enhanced oxidation of GaAs
9. A GaAs MOSFET with a liquid phase oxidized gate
10. Fabrication of depletion-mode GaAs MOSFET with a selective oxidation process by using metal as the mask