Stencil mask ion implantation technology

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 183-188

  Shibata, Takeshi ^a   Suguro, Kyoichi ^a   Sugihara, Kazuyoshi ^a   Nishihashi, Tsutomu ^b   Fujiyama, Junki ^b   Sakurada, Yuzo ^b  

^a TOSHIBA CORPORATION   (Japan)

^b ULVAC INC   (Japan)

Author keywords

Agile fab; Damascene metal gate; Ion implantation; MOSFET; SMIT; Stencil mask

Indexed keywords

ION IMPLANTATION; MASKS; MOSFET DEVICES; PHOTOLITHOGRAPHY; PHOTORESISTS; SILICON WAFERS; THRESHOLD VOLTAGE; TRANSISTORS; VOLTAGE CONTROL;

STENCIL MASK ION IMPLANTATION TECHNOLOGY (SMIT);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036565638     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999589     Document Type: Article

References (5)

1. Stencil mask ion implantation technology for high performance MOSFET
2. Ion-graphy implanter with stencil mask
3. Lithography-less ion implantation technology for Agile Fab
4. New charge control technology by stencil mask ion implantation
5. New charge control technology by stencil mask ion implantation