A numerical analysis of a CMOS images sensor with a simple fixed-pattern-noise-reduction technology

IEEE Transactions on Electron Devices

Volumn 49, Issue 5, 2002, Pages 746-753

  Yonemoto, Kazuya ^a   Sumi, Hirofumi ^b  

^a WASEDA UNIVERSITY   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

Active pixel sensor (APS); CMOS image sensor; Correlated double sampling (CDS); Fixed pattern noise (FPN); I V converter; Image lag; Linearity; Pinned photodiode

Indexed keywords

CHARGE TRANSFER; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CONVERTERS; GATES (TRANSISTOR); IMAGE SENSORS; NOISE ABATEMENT; NUMERICAL ANALYSIS; PHOTODIODES; SEMICONDUCTOR DEVICE STRUCTURES; THRESHOLD VOLTAGE;

ACTIVE PIXEL SENSOR; AMPLIFICATION FACTOR; CORRELATED DOUBLE SAMPLING; CURRENT MIRROR CIRCUIT; FIXED PATTERN NOISE; HOLE ACCUMULATION DIODE; IMAGE LAG;

CMOS INTEGRATED CIRCUITS;

EID: 0036564306     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.998580     Document Type: Article

References (5)

1. A 48 kframe/s CMOS image sensor for real-time 3-D sensing and motion detection
2. A signal-processing CMOS image sensor using a simple analog operation
3. 128 × 128 CMOS photodiode-type active pixel sensor with on-chip timing, control and signal chain electronics
4. 2 square pixel CMOS image sensor for digital still camera application
5. A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode