Integrating scan into hierarchical synthesis methodologies

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 751-756

  Beausang, James ^a   Ellingham, Chris ^a   Robinson, Markus ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

DESIGN FOR TEST (DFT);

INTEGRATED CIRCUIT TESTING;

EID: 0030407214     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)