IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 55-63

  Vermeulen, Bart ^a   Waayers, Tom ^a   Bakker, Sjaak ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; FIELD PROGRAMMABLE GATE ARRAYS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; PROGRAM DEBUGGING; STANDARDS;

BYPASS MULTIPLEXER; DIGITAL SYSTEM CHIPS; MULTIPLE CORE DEBUG;

INTEGRATED CIRCUIT TESTING;

EID: 0036446074     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. ARM Ltd., "IHI-0011A - AMBA Specification Rev2.0", May 1999, ARM Ltd., http://www.arm.com
2. IEEE P1500, "Standard for Embedded Core Test (SECT)" homepage. http://grouper.ieee.org/groups/1500/.
3. IEEE Computer Society. "IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Std. 1149.1-2001", IEEE, New York, 2001.
4. E.-J. Marinissen et al., "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores", in Proceedings International Test Conference, IEEE Computer Society Press, Washington, DC, pp. 284-293, October 1998.
5. L. D. Whetsel, "An IEEE 1149.1 Based Test Access Architecture For ICs With Embedded Cores". in Proceedings International Test Conference, pp. 69-78, Washington, D.C., USA, 1997
6. S.F. Oakland, "Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits", in Proceedings International Test Conference, pp. 628-637. Atlantic City, NJ, USA, 2000
7. N. Jarwala, "Designing 'Dual Personality" "IEEE 1149.1 Compliant Multi-Chip Modules", in Proceedings International Test Conference, pp. 446-455, USA, 1994