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Volumn , Issue , 2002, Pages 31-39

A faster distributed arithmetic architecture for FPGAs

Author keywords

Carry propagation; Cost performance analysis; DALUT; Distributed arithmetic; XC4000

Indexed keywords

COMPUTATIONAL METHODS; COST BENEFIT ANALYSIS; DIGITAL SIGNAL PROCESSING; DISTRIBUTED COMPUTER SYSTEMS; LOGIC DESIGN;

EID: 0036382550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503048.503054     Document Type: Conference Paper
Times cited : (13)

References (12)
  • 1
    • 0024700020 scopus 로고    scopus 로고
    • Applications of distributed arithmetic to digital signal processing: A tutorial review
    • S.A. White. Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review. IEEE ASSP Magazine, Vol. 6, No. 3, pp. 4-19.
    • IEEE ASSP Magazine , vol.6 , Issue.3 , pp. 4-19
    • White, S.A.1
  • 2
    • 0029359939 scopus 로고
    • A distributed arithmetic approach to designing scalable DSP chips
    • August 17
    • B. New, "A Distributed Arithmetic Approach to Designing Scalable DSP Chips", Electronic Design News, August 17, 1995.
    • (1995) Electronic Design News
    • New, B.1
  • 5
    • 0031340034 scopus 로고    scopus 로고
    • Efficient implementation of the DCT on custom computers
    • Kenneth L. Pocek and Jeffrey Arnold, editors, Los Alamitos, CA, April
    • N.W. Bergman, Y.Y. Chung, B.K. Gunther. Efficient Implementation of the DCT on Custom Computers. In Kenneth L. Pocek and Jeffrey Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 244-245, Los Alamitos, CA, April 1997.
    • (1997) IEEE Symposium on FPGAs for Custom Computing Machines , pp. 244-245
    • Bergman, N.W.1    Chung, Y.Y.2    Gunther, B.K.3
  • 6
  • 8
    • 0002998222 scopus 로고
    • Dependence analysis and architecture design for bit-level algorithms
    • W. Shang, B. W. Wah. Dependence Analysis and Architecture Design for Bit-Level Algorithms. Intl. Conf. On Parallel Process, vol. I, pp. 30-38, 1993.
    • (1993) Intl. Conf. on Parallel Process , vol.1 , pp. 30-38
    • Shang, W.1    Wah, B.W.2
  • 9
    • 0033733825 scopus 로고    scopus 로고
    • Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques
    • March
    • Zhen Luo and Margaret Martonosi. Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques. IEEE Transactions on Computers, Vol. 49, No. 3, March 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , Issue.3
    • Luo, Z.1    Martonosi, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.