ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 427-430

  Ker, Ming Dou ^a   Lo, Wen Yu ^a   Lee, Chien Ming ^a   Chen, Chia Pei ^a   Kao, Hong Sing ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIODES; ELECTRIC DISCHARGES; ELECTRIC IMPEDANCE; ELECTRIC RESISTANCE; LEAKAGE CURRENTS; PERFORMANCE; SPURIOUS SIGNAL NOISE;

PROTECTION CIRCUITS;

SIGNAL RECEIVERS;

EID: 0036316886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology
2. A sub-1-dB NF ±2.3-kV ESD-protected 900-MHz CMOS LNA
3. A 0.8dB NF ESD-protected 9mW CMOS LNA
4. High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection
5. Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process
6. Diode network used as ESD protection in RF applications
7. Distributed ESD protection for high-speed integrated circuits
8. Analysis and design of ESD protection circuits for high-frequency/RF applications
9. ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications