A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-μm CMOS process

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 463-466

  Wong, Joseph M C ^a   Luong, Howard C ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DYNAMIC LOADS; FREQUENCY DIVIDING CIRCUITS; SPURIOUS SIGNAL NOISE;

PHASE NOISE;

FREQUENCY DOUBLERS;

EID: 0036314131     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Design and analysis of a ±1V CMOS four-quadrant analogue multiplier
2. A 2-V 5.1-5.8-GHz image-reject receiver with wide dynamic range
3. A novel high-speed ring oscillators for multiphase clock generation using negative skewed delay scheme
4. 2-V 900-MHz quadrature coupled LC oscillator with improved amplitude and phase matchings