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Volumn 45, Issue 5, 1998, Pages 584-591

A formal technique for hardware interface design

Author keywords

Communication synthesis; DSP systems; Hardware software codesign; Interface generation; Real time

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; INTERFACES (COMPUTER); PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

EID: 0032069573     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.673640     Document Type: Article
Times cited : (16)

References (13)
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    • The Chinook hardware/software co-synthesis system, in
    • P. H. Chou, R. B Ortega, and G. Boriello, The Chinook hardware/software co-synthesis system, in Proc. ISSS, 1995, pp. 280-287.
    • (1995) Proc. ISSS , pp. 280-287
    • Chou, P.H.1    Ortega, R.B.2    Boriello, G.3
  • 7
    • 0027662042 scopus 로고
    • Interface optimization for concurrent systems under timing constraints
    • Sept.
    • D. Filo, D. C. Ku, C. N. Coelho, and G. De Micheli, Interface optimization for concurrent systems under timing constraints, IEEE Trans. VLSI Syst., vol. 1, pp. 268-281, Sept. 1993.
    • (1993) IEEE Trans. VLSI Syst. , vol.1 , pp. 268-281
    • Filo, D.1    Ku, D.C.2    Coelho, C.N.3    De Micheli, G.4
  • 8
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    • Gupta, R.K.1    Coelho, C.N.2    De Micheli, G.3
  • 9
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    • Protocol generation for communication channels, in
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  • 10
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    • Synthesis of system level bus interfaces
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  • 12
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    • Massively parallel computing systems with real time constraints: The algorithm architecture adequation, in
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    • Sorel, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.