A novel floating-gate multiple-valued CMOS full-adder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Berg, Y ^a   Aunet, S ^a   NAEss O ^a   Hagen, O ^a   Hovin M ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; LOGIC GATES; MOSFET DEVICES; SWITCHING FUNCTIONS; VLSI CIRCUITS;

BINARY LOGIC; EQUILIBRIUM CURRENT; EQUILIBRIUM STATE; FLOATING GATE; MULTIPLE VALUED LOGIC; RIPPLE ADDER; ULTRA LOW VOLTAGE;

ADDERS;

EID: 0036290590     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. The prospects of multivalued logic systems
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3. Ultra low-voltage/low-power digital floating-gate circuits
4. Programming floating-gate circuits with UV-activated conductances
5. UV-activated conductances allow for multiple scale learning
6. Floating-gate CMOS differential analog inverter for ultra low-voltage applications
7. A novel radix R multiple-valued to binary converter in floating-gate CMOS
8. Multiple-input neuron MOS operational amplifier for voltage-mode multivalued full adders