Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices

IEEE Transactions on Electron Devices

Volumn 49, Issue 1, 2002, Pages 67-71

  Wang, Howard Chih Hao ^b,c   Wang, Chih Chiang ^b   Diaz, Carlos H ^a,b   Liew, Boon Khim ^b   Sun, Jack Yuan Chen ^a,b   Wang, Tahui ^a,c  

^a IEEE

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Hot carriers; MOS devices; Transient enhanced diffusion

Indexed keywords

ARSENIC; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FIELDS; ELECTRIC POTENTIAL; HOT CARRIERS; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTOR DOPING;

CARRIER RESISTANCE; CURRENT FLOW DISTRIBUTIONS; LIGHTLY DOPED DRAIN; TRANSIENT ENHANCED DIFFUSION;

CMOS INTEGRATED CIRCUITS;

EID: 0036253281     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.974751     Document Type: Article

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