0.25 μm CMOS/SIMOX PLL clock generator embedded in a gate array LSI with 5 to 400 MHz lock range

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 41-44

  Sutoh, Hiroki ^a   Yamakoshi, Kimihiro ^a   Ino, Masayuki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY RESPONSE; LSI CIRCUITS; PULSE GENERATORS; SYNCHRONIZATION; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATORS;

PHASE LOCKED LOOPS;

EID: 0030689965     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)