An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 12, Issue 3, 1998, Pages 171-185

  Aktouf, C ^a,c,d,e   Robach, C ^a,d,f   Marinescu, A ^a,d,g   Mazare, G ^b,d,h,i  

^a Grenoble Institute of Technology   (France)

^b INP Grenoble ENSIMAG   (France)

^c UNIV GRENOBLE ALPES   (France)

^d GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^e UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^f CNRS   (France)

^g UNIVERSITY OF BUCHAREST   (Romania)

^h VLSI   (France)

ⁱ ECOLE CENTRALE PARIS   (France)

Author keywords

Built in self test; Diagnosis; IEEE 1149.1; MIMD architectures; Routing test

Indexed keywords

BUILT-IN SELF TEST; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; ROUTERS; STANDARDS; VECTORS; VLSI CIRCUITS;

MASSIVELY PARALLEL ARCHITECTURES; MULTIPLE INSTRUCTION MULTIPLE DATA (MIMD) ARCHITECTURES;

INTEGRATED CIRCUIT TESTING;

EID: 0032094510     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008216431810     Document Type: Article

References (20)

1. L.R. Goke and G.L. Lipovski, "Banyan Networks for Partitioning Multiprocessor Systems," Proc. of the First Annual Computer Architecture Conference, 1973, pp. 21-28.
2. "Fine-Grain Concurrent Computation," Caltech Computer Science TR. 5242: TR. 87.
3. P.M. Kogge, "Execube - A New Architecture for Scalable mpps," Proc. of the International Conference on Parallel Processing, 1994, pp. 77-84.
4. C. Aktouf, G. Mazaré, and C. Robach, "Memory Testing in a Massively Parallel Machine," Microprocessing and Microprogramming: The Euromicro Journal, Vol. 38, Nos. 1-5, pp. 245-252, Sept. 1993.
5. C. Aktouf, C. Robach, J. Johansson, and G. Mazaré, "Functional Testing and Reconfiguration of Massively MIMD Machines," Proc. of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993, pp. 72-79.
6. C.M. Maunder and R.E. Tulloss, "The Test Access Port and Boundary-Scan Architecture," IEEE Computer Society Press, 1990.
7. D. Landis and P. Singh, "Optimal Placement of IEEE 1149.1 Port and Boundary-Scan Resources for Wafer Scale Integration," Proc. of the International Test Conference, 1990, pp. 120-126.
8. D. Landis, "A Self-Test System Architecture for Reconfigurable WSI," Proc. of the International Test Conference, 1989, pp. 275-281.
9. Y. Zorian, "A Structured Approach to Complex VLSI Test Using BIST and Boundary-Scan," Proc. of ATE West Symposium, 1990, p. 69.
10. C. Aktouf, Y. Latrous, and G. Mazaré, "Asynchronous Processor Network: The Project of the Polytechnique Institute of Grenoble," Supercomputer Journal, Vol. XII-2, pp. 20-25, 1996.
11. C. Aktouf, C. Robach, and A. Marinescu, "A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1," Proc. of the International Test Conference, Washington, 1995, pp. 781-788.
12. F. Boiteux and M. Robichon, "Réalisation d'une Interface Matérielle et Logicielle Entre un Ordinateur Hôte Macintosh II et un Réseau Parallèle Cellulaire," Master report, ENSIMAG-ENSERG, June 1991.
13. C.M. Maunder and R.E. Tulloss, "An Introduction to the Boundary-Scan Standard: ANSI/IEEE Std. 1149.1," Journal of Electronic Testing: Theory and Applications, Vol. 2, pp. 27-41, 1991.
14. A. Dahbura and M.U. Uyar, "An Optimal Test Sequence for the JTAG/IEEE P.1149.1 Test Access Port Controller," Proc. of the International Test Conference, 1989, pp. 55-62.
15. K.E. Batcher, "Sorting Networks and their Applications," Proc. of AFIPS, 1968, pp. 307-314.
16. T. Sheu, C. Das, and M. Irwin, "Distributed Fault Diagnosis in the Butterfly Parallel Processor," Proc. of the International Conference on Parallel Processing, 1989, pp. 172-175.
17. C. Aktouf, G. Mazaré, C. Robach, and R. Velazco, "A Practical Approach for the Diagnosis of MIMD Network," Proc. of the First Asian Test Symposium, 1992, pp. 387-390.
18. V.K. Agarwal, B. Nadeau-Dostie, and Ph.S. Wilcox, "A Scanbased BIST Technique Using Pair-wise Compare of Identical Components," Proc. of the International Test Conference, 1991, pp. 225-230.
19. A. Marinescu, "Test de Routage d'une Architecture Massivement Parallèle Basée sur le Boundary-Scan," Master's thesis, Laboratoire de Génie Informatique, Grenoble, France, July 1994.
20. W. Dally et al., "The J-Machine: A Fine Grain Concurent Computer," Proc. of the IFIP Congress, 1989, pp. 1147-1153.