A 64 MHz ΣΔ ADC with 105 dB IM3 distortion using a linearized replica sampling network

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 224-225+462+213

  Gupta, Sandeep K ^a   Brooks, Todd L ^a   Fong, Victor ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; GAIN CONTROL; LINEAR NETWORKS; SIGNAL DISTORTION; SPURIOUS SIGNAL NOISE;

NOISE CANCELLATION;

ANALOG TO DIGITAL CONVERSION;

EID: 0036114025     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 90 dB SNR 2.5 MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8X oversampling ratio
2. A cascaded Sigma-Delta Pipeline A/D converter with 1.25 Mhz signal bandwidth and 89 dB SNR
3. A 15 b resolution Delta Sigma ADC in a 1um CMOS technology
4. A 3.3 V, 12 b, 50 MSample/s A/D converter in 0.6 mm CMOS with over 80 dB SFDR