A sense and restore technique for multilevel DRAM

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 7, 1996, Pages 483-486

  Gillingham, Peter ^a,b  

^a IEEE   (Canada)

^b MOSAID Technologies Inc   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG STORAGE; COMPUTER SIMULATION; DIFFERENTIAL AMPLIFIERS;

AMPLIFIER REFERENCE LEVELS; CHARGE REDISTRIBUTION TECHNIQUES; DYNAMIC RANDOM ACCESS MEMORY (DRAM) MEMORY CELL; LOCAL BITLINES; WORDLINE DRIVERS;

RANDOM ACCESS STORAGE;

EID: 0030196569     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.508424     Document Type: Article

References (8)

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2. Y. Nakagome et al., A high S/N design on multilevel storage dynamic memory,' in Extended Abstracts of the 17th Conf. Solid State Devices and Materials, Tokyo, Aug. 1985, pp. 45-48.
3. T. Fnruyama et ai. An experimental 2-hit/cell storage DRAM for macrocell or memory-on-logic application, IEEEJ. Solid-Stale Circuits, vol. 24, pp. 388-393, Apr. 1989.
4. Y. Ohta et al, A novel memory cell architecture for high-density DRAM's, in 1989 Symp. VLSI Circuits Dig. Tech. Papers, pp. 101-102.
5. T Mano el al., .Snhmicron VLSI memory circuits, ISSCC Dig. Te.c'n. Papers, Feb. 1983, pp. 234-235.
6. T. Kawahara el al., A high speed, small area, threshold-voltagemismatch compensation sense amplifier for gigabit-scale DRAM arrays,'' IEEE J. Solid-Stale Circuits, vol. 27, pp. 816-823, July 1993.
7. Y. Watanabe el al., Offset compensating bit-line sensing scheme for high density DRAM's, IEEE J. Solid-Siate Circuits, vol. 29, pp. 9-13. Jan. 1994.
8. T. Hasegavva el al., An experimental DRAM with a NAND-structured cell, IEEE]. Solid-Stale Circuits, vol. 28, pp. 1099-1104, Nov. 1993.