Advanced Cu CMP defect excursion control for leading edge micro-processor manufacturing

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2002, Pages 92-97

  Stoeckl, Peter ^a   Saville, Barry ^b   Kavanagh, Jim ^b   Dellwig, Thilo ^b  

^a IBM MICROELECTRONICS   (United States)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; COST EFFECTIVENESS; INTEGRATION; MATHEMATICAL MODELS; MICROELECTRONIC PROCESSING; SILICON WAFERS;

NUISANCE DEFECTS; SINGLE WAFER EXCURSION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0036073368     PISSN: 1523553X     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASMC.2002.1001581     Document Type: Article

References (4)

1. Review sample shaping through the simultaneous use of multiple classification technologies
2. In-line monitoring of copper defects
3. Development of an optimal sampling strategy for wafer inspection