Design of an one-cycle decompression hardware for performance increase in embedded systems

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 34-39

  Lekatsas, Haris ^a   Henkel, Jörg ^a   Jakkula, Venkata ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; INTERFACES (COMPUTER); PERSONAL DIGITAL ASSISTANTS; PROGRAM PROCESSORS;

DECOMPRESSION HARDWARE;

EMBEDDED SYSTEMS;

EID: 0036058774     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513918.513929     Document Type: Conference Paper

References (10)

1. Selective instruction compression for memory energy reduction in embedded systems
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3. Instruction code compression for application specific VLIW processors based on automatic field partitioning
4. Reducing code size with run-time decompression
5. Code density optimization for embedded DSP processors using data compression techniques
6. Instruction encoding techniques for area minimization of instruction ROM
7. Executing compressed programs on an embedded RISC architecture
8. An object code compression approach to embedded processors