Fault simulation and response compaction in full scan circuits using HOPE

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 1, Issue , 2002, Pages 607-612

  Das, Sunil R ^a   Assaf, Mansour H ^a   Petriu, Emil M ^a   Jone, Wen Ben ^a  

^a UNIVERSITY OF OTTAWA   (Canada)

Author keywords

Built in self test (BIST); Circuit under test (CUT); Detectable error probability estimates; Fault simulation using HOPE; Hamming distance; Optimal sequence mergeability; Response compaction; Sequence weights; Single stuck line faults; Space compactor

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; ERROR ANALYSIS; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

CIRCUIT UNDER TEST; DETECTABLE ERROR PROBABILITY ESTIMATES; FAULT SIMULATION; FULL SCAN CIRCUITS; HAMMING DISTANCE; OPTIMAL SEQUENCE MERGEABILITY; RESPONSE COMPACTION; SEQUENCE WEIGHTS; SINGLE STUCK LINE FAULTS; SOFTWARE PACKAGE HOPE;

BUILT-IN SELF TEST;

EID: 0036054125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities
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6. Built-in self-test techniques
7. HOPE: An efficient parallel fault simulator for synchronous sequential circuits
8. A new framework for designing and analyzing BIST techniques and zero aliasing compression
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10. Testing computer hardware through compression in space and time
11. Reducing the MISR size
12. Test response compaction for built-in self-testing
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