Fragile porous low-k/copper integration by using electro-chemical polishing

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 32-33

  Takahashi, Shingo ^a   Tai, Kaori ^a   Ohtorii, Hiizu ^a   Komai, Naoki ^a   Segawa, Yuji ^a   Horikoshi, Hiroshi ^a   Yasuda, Zenya ^a   Yamada, Hiroshi ^a   Ishihara, Masao ^a   Nogami, Takeshi ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; COPPER; ELECTRIC RESISTANCE; ELECTROLYTIC POLISHING; PERMITTIVITY; POROUS MATERIALS; SILICA;

LOW PRESSURE POLISHING;

DIELECTRIC MATERIALS;

EID: 0036053621     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Newly developed electro-chemical polishing process of copper as replacement of CMP suitable for damascene copper inlaid in fragile low-k dielectrics