A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 166-167

  Celik, Muhsin ^a   Krishnan, Srinath ^a   Fuselier, Mark ^a   Wei, Andy ^a   Wu, David ^a   En, Bill ^a   Cave, Nigel ^a   Abramowitz, Peter ^a   Min, Byoung ^a   Pelella, Mario ^a   Yeh, Ping ^a   Burbach, Gert ^a   Taylor, Bill ^a   Jeon, Yongjoo ^a   Qi, Wen Jie ^a   Li, Ruigang ^a   Conner, Jim ^a   Yeap, Geoffrey ^a   Woo, Michael ^a   Mendicino, Mike ^a   Karlsson, Olov ^a   Wristers, Dirk ^a   more..

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; OSCILLATORS (ELECTRONIC); SEMICONDUCTING FILMS; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; TRANSMISSION ELECTRON MICROSCOPY;

FLOATING BODY EFFECTS (FBE); PARTIALLY DEPLETED (PD) TRANSISTORS;

TRANSISTORS;

EID: 0036047593     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)