Analytical model for thermal instability of low voltage power MOS and S.O.A. in pulse operation

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2002, Pages 269-272

  Spirito, P ^a   Breglio, G ^a   D'Alessandro, V ^a   Rinaldi, N ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

HEAT RESISTANCE; POWER ELECTRONICS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; THERMODYNAMIC STABILITY;

SAFE OPERATING AREA (SOA);

MOS DEVICES;

EID: 0036045176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Electro-thermal instability in low voltage power MOS: Experimental characterization
2. Avalanche induced thermal instability in LDMOS transistors
3. Experimental detection of time dependent temperature maps in power bipolar transistors
4. Thermal mapping and 3D numerical simulation of new cellular power MOS affected by electro-thermal instability
5. On the modeling of the transient thermal behavior of semiconductor devices