A digital calibration technique for pipelined analog-to-digital converters

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 1, Issue , 2002, Pages 713-717

  Furuta, Masanori ^a   Kawahito, Shoji ^a   Miyazaki, Daisuke ^a  

^a SHIZUOKA UNIVERSITY   (Japan)

Author keywords

Digital calibration; Error measurement; Parallel pipelined ADC; Pipelined ADC

Indexed keywords

CALIBRATION; DIGITAL SIGNAL PROCESSING; MEASUREMENT ERRORS; PIPELINE PROCESSING SYSTEMS; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO;

DIGITAL CALIBRATION; PEAK DIFFERENTIAL NONLINEARITY; PEAK INTEGRAL NONLINEARITY; PIPELINE ANALOG TO DIGITAL CONVERTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 0036044560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 10-bit 200-MS/s CMOS parallel pipelined A/D converter
2. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3u-m CMOS
3. A low-power 12-b analog-to-digital converter with on-chip precision trimming
4. A digital background calibration technique for time-interleaved analog-to-digital converters
5. A single-ended 12-bit 20Msample/s self-calibrating pipelined A/D converter
6. A 12-b 600ks/s digitally self-calibrated pipelined algorithmic ADC