Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity

Performance Evaluation Review

Volumn 30, Issue 1, 2002, Pages 252-253

  Cook, Jeanine ^a   Oliver, Richard L ^a   Johnson, Eric E ^a  

^a NEW MEXICO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ESTIMATION; MATHEMATICAL MODELS;

ADAPTIVE-MODEL METHOD; MICROARCHITECTURE COMPLEXITY; SOFTWARE PACKAGE; SOFTWARE PACKAGE SIMPLESCALAR; SOFTWARE PACKAGE SWEEP;

RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0036041833     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/511399.511366     Document Type: Conference Paper

References (5)

1. A time-stamping algorithm for efficient performance estimation of superscalar processors
2. HLS: Combining statistical and symbolic simulation to guide microprocessor designs
3. Fast out-of-order processor simulation using memoization