A high speed scheduler/controller for unbuffered banyan networks

Computer Communications

Volumn 24, Issue 12, 2001, Pages 1158-1169

  Salisbury, C ^a   Melhem, R ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b University of Pittsburgh   (United States)

Author keywords

Banyan network; Circuit switching; Communication switch architecture

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; CONGESTION CONTROL (COMMUNICATION); DATA TRANSFER; TELECOMMUNICATION TRAFFIC;

BANYAN NETWORKS; COMMUNICATION SWITCH ARCHITECTURE;

PACKET NETWORKS;

EID: 0035879579     PISSN: 01403664     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0140-3664(00)00329-7     Document Type: Article

References (15)

1. Analysis of replicated banyan networks with input and output queuing for ATM switching
2. Design of a gigabit ATM switch
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4. A new parallel banyan ATM switch architecture
5. Performance analysis of a multicast switch
6. The performance of multistage interconnection networks for multiprocessors
7. The Tiny Tera: A Packet Switch Core
8. Scheduling multicast cells in an input-queued switch
9. Reconfiguration with time division multiplexing MINs for multiprocessor communications
10. Distributed path management in switched optical banyan networks
11. Space and time redundant broadband packet switch
12. Fast packet switch architectures for broadband integrated services digital networks
13. Architecture, performance, and implementation of the tandem banyan fast packet switch
14. Architecture of a packet switch based on banyan switching network with feedback loops
15. A new ATM switch design using wrapped around multiple WAM banyan network