Optimisation for improved short-channel performance of surrounding/cylindrical gate MOSFETs

Electronics Letters

Volumn 37, Issue 8, 2001, Pages 533-534

  Kranti, A ^a   Rashmi, ^a   Haldar, S ^b   Gupta, R S ^a  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION; POISSON EQUATION; THIN FILMS; ULSI CIRCUITS;

SHORT CHANNEL EFFECTS; SURROUNDING GATE MOSFET;

MOSFET DEVICES;

EID: 0035848734     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010340     Document Type: Article

References (5)

1. YAN, R.H., QURMAZD, A., and LEE, K.F.: 'Scaling the Si MOSFET: from bulk to SOI to bulk', IEEE Trans. Electron Devices, 1992, 39, (7), pp. 1704-1710
2. TAKATO, H., SUNOUCHI, K., OKABE, N., NITAYAMA, A., HIEDA, K., HORIGUCHI, F., and MASUOKA, F.: 'Impact of surrounding gate transistor (SGT) for ultra high density LSIs', IEEE Trans. Electron Devices, 1991, 38, (3), pp. 573-578
3. AUTH, C.P., and PLUMMER, J.D.: 'Scaling theory for cylindrical fully-depleted, surrounding gate MOSFETs', IEEE Electron Device Lett., 1997, 18, (2), pp. 74-76
4. RATNAKUMAR, K.N., and MEINDL, J.D.: 'Short channel MOST threshold voltage model', IEEE J. Solid-State Circuits, 1982, 17, (5), pp. 937-947
5. ENDOH, T., NAKAMURA, T., and MASUOKA, F.: 'An analytical steady-state current-voltage characteristics of short channel fully depleted surrounding gate transistor (FD-SGT)', IEICE Trans. Electron., 1997, E80-C, (7), pp. 911-917