High-density multi-layer thin-film packaging technology for high-performance ASIC chips

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4587, Issue , 2001, Pages 242-247

  Kikuchi, Katsumi ^a   Shimoto, Tadanori ^a   Honda, Hirokazu ^a   Kata, Keiichiro ^a   Matsui, Koji ^a   Morishige, Sueo ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Area array; Flip chip; High pin count; Metal base; Multi layer thin film; Wet etching

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ETCHING; FLIP CHIP DEVICES; GLASS TRANSITION; LSI CIRCUITS; MULTILAYERS; SUBSTRATES; THIN FILMS;

WET ETCHING;

CHIP SCALE PACKAGES;

EID: 0035770408     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. International Technology Roadmap for Semiconductors 1999 Edition, SIA, 1999.
2. R.R. Tummala, E.J. Rymaszewski, and A.G. Klopfenstein, "Microelectronics Packaging Handbook", Part II, pp.658, 1996.
3. R. Enomoto, M. Asai, and N. Hirose, "High density MLB using additive and build-up process", Proceedings of the 1998 IMAPS, San Diego, California, November 1-4, pp.403-408, 1998.