Evaluating device design rules based on lithographic capability

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4346, Issue 2, 2001, Pages 917-924

  Warrick, Scott ^a   Smith, Chris ^a   Monroe, Matt ^b   Casteel, Carroll ^a   Zaleski, Mark ^a  

^a MOTOROLA INC   (United States)

^b Digital Optics Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; MICROPROCESSOR CHIPS;

CRITICAL DIMENSIONS;

LITHOGRAPHY;

EID: 0035758765     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.435792     Document Type: Article

References (4)

1. Levinson, H.J. Preil, M.E. Lord, P.J., "Minimization of total overlay errors on product wafers using an advanced optimization scheme", Proceedings of the SPIE, Vol. 3051, pp. 362-73, 1997.
2. B. Katz, et al, "Evaluation of High Numerical Aperture Wide-Field Steppers for 0.35 Micron Design Rules", Proceedings of the SPIE, Vol. 1674, pp. 725-40, 1992.
3. Harry Sewell, Scott Smith, Dan Galburt, "0.10-Micron overlay for DRAM production using Step and Scan", Proceedings of the SPIE, Vol. 1264, pp. 252-62, 1990.
4. nd ed. Chapter 29, Irwin, Homewood Ill., 1985.