Device characteristics of a 30-V-class thin-film SOI power MOSFET

IEEE Transactions on Electron Devices

Volumn 43, Issue 5, 1996, Pages 746-752

  Matsumoto, Satoshi ^a,b   Kim, Il Jung ^a,b   Sakai, Tatsuo ^a,b   Fukumitsu, Takao ^b   Yachi, Toshiaki ^a,b  

^a IEEE

^b NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITANCE MEASUREMENT; ELECTRIC BREAKDOWN; ELECTRIC NETWORK TOPOLOGY; ELECTRIC PROPERTIES; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS;

BREAKDOWN VOLTAGE; LINEAR GATE TOPOLOGY; PARASITIC CAPACITANCE; SPECIFIC ON RESISTANCE; TUNGSTEN POLYCIDE GATE;

MOSFET DEVICES;

EID: 0030151515     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.491251     Document Type: Article

References (12)

1. B. J. Baliga, "Revolutionary innovations in power discrete devices," in Tech. Dig. Int. Electron Devices Mtg., 1980, pp. 102-105.
2. G. E. Norman, Ed., Silicon on Insulator for VLSI and VHSIC. London: Academic, 1982, vol. 4, p. 1.
3. S. Marchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, and R. Pinker, "Realization of high breakdown voltage (>700 V) in thin SOI devices," in Proc. 3rd Int. Symp. Power Semiconductor Devices & ICs, 1991, pp. 31-35.
4. Y. S. Hung and B. J. Baliga, "Extension of resurf principle to dielectrically isolated power devices," in Proc. 3rd Int. Symp. Power Semiconductor Devices & ICs, 1991, pp. 27-30.
5. Q. Lu, P. Ratnam, and C. A. T. Salama, "Novel high-voltage silicon-on-insulator MOSFET's," Solid State Electronics, vol. 13, pp. 1745-1750, 1992.
6. R. Constapel and J. Korec, "Forward blocking characteristics of SOI power device at high temperatures," in Proc. 6th Int. Symp. Power Semiconductor Devices & ICs, 1994, pp. 117-121.
7. T. Matsudai and A. Nakagawa, "Simulation of a 700 V high-voltage device structure on a thin SOI - Substrate bias effect on SOI device," in Proc. 4th Int. Symp. Power Semiconductor Devices & ICs, 1992, pp. 272-277.
8. S. Matsumoto and H. Yoshino, "Device simulation of a thin-film silicon on insulator power metal-oxide-semiconductor field-effect transistor for structure optimization," Jpn. J. Appl. Phys., vol. 33, pp. 519-523, 1994.
9. S. Matsumoto, I.-J. Kim, T. Sakai, T. Fukumitsu, and T. Yachi, "Switching characteristics of a thin-film SOI power MOSFET," Jpn. J. Appl. Phys., vol. 34, pp. 817-821, 1995.
10. 2 layers formed by oxygen implantation into silicon," Electron. Lett, vol. 14, pp. 593-594, 1978.
11. K. Shenai, "High frequency MOSFET's fabricated using selectively deposited LPCVD tungsten," Electron. Lett., vol. 25, pp. 1033-1034, 1989.
12. I.-J. Kim, S. Matsumoto, T. Sakai, and T. Yachi, "New power device figure of merit for high-frequency applications," in Proc. 7th Int. Symp. Power Semiconductor Devices & ICs, 1995, pp. 309-314.