Formal verification of embedded SoC

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 769-772

  Wang, Bin ^a   Lin, Zheng Hui ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; PROGRAM ASSEMBLERS; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTOR DEVICE MODELS;

FORMAL VERIFICATION; HANDSHAKING PROTOCOL; SMV MODEL; SYSTEM ON A CHIP;

MICROPROCESSOR CHIPS;

EID: 0035722481     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (7)

1. A hierarchical approach to the formal verification of embedded systems using MDGs
2. Modelling and verification of embeded systems using cadence SMV
3. Getting started with SMV
4. Hands-on computer architecture - Teaching processor and integrated systems design with FPGAs gray research
5. Verifying hardware in its software context: Computer-aided design, 1997
6. Verification of embedded systems using a petri net based representation: Systems synthesis, 2000