Gate-induced drain-leakage in buried-channel PMOS - A limiting factor in development of low-cost, high-performance 3.3-V, 0.25-μm technology

IEEE Electron Device Letters

Volumn 19, Issue 9, 1998, Pages 354-356

  Ghodsi, Ramin ^a,b   Sharifzadeh, Shahin ^a,b   Majjiga, Jithender ^b  

^a IEEE   (United States)

^b CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MANUFACTURE;

GATE-INDUCED DRAIN-LEAKAGE (GIDL);

MOS DEVICES;

EID: 0032167122     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.709642     Document Type: Article

References (5)

1. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu., "The impact of gate-induced current on MOSFET scaling," in IEDM Tech. Dig., 1987, p. 718.
2. H. J. Wann, P. K. Ko, and C. Hu, "Gate-induced band-to-band tunnelling leakage current in LDD MOSFET's," in IEDM Tech. Dig., 1992, p. 147.
3. +-poly PMOS devices," IEEE Electron Device Lett., vol. 17, p. 285, June 1996.
4. C. Mazure, C. Gunderson, and B. Roman, "Impact of LDD spacer reduction on MOSFET performance for sub-μm gate/spacer pitches," in IEDM Tech Dig., 1992, p. 893.
5. C. Y. Wong, J. Piccirillo, A. Bhattacharyya, Y. Taur, and H. I. Hanafi, "Sidewall oxidation of polycrystalline-silicon gate," IEEE Electron Device Lett., vol. 10, p. 421, Sept. 1989.