Real impact of W/WNx/Poly-Si gate stack in volume production of high density DRAM

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 615-618

  Kim, Il Gweon ^a   Kim, Nam Sung ^a   Choy, Jun Ho ^a   Lee, Byung Hak ^a   Sung, Yong Gue ^a   Kim, Jong Hwan ^a   Cho, Jin Hee ^a   Kim, Dong Chan ^a   Kim, Kee Soo ^a   Choi, Jo Bong ^a   Choi, Se Kyoung ^a   Kweon, Young Woo ^a   Kwon, Ho Yup ^a   Park, Dae Guy ^a   Park, Joo Seog ^a   Park, Dae Young ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ETCHING; HOT CARRIERS; OXIDATION; POLYSILICON; TRANSMISSION ELECTRON MICROSCOPY; TUNGSTEN; TUNGSTEN COMPOUNDS;

CELL DEGRADATION; POLYCIDE GATE STACK; POLYMETAL GATE STACK;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035715831     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979584     Document Type: Article

References (3)

1. In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WNx on polycrystalline Si
2. Roles of oxide trapped charge and generated interface states on GIDL under hot-carriers stressing
3. Hot-carrier-induced gate capacitance variation and its impact on DRAM circuit functionality