A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform

Technical Digest-International Electron Devices Meeting

Volumn , Issue , 2001, Pages 227-230

  Ohnishi, K ^a   Tsuchiya, R ^a   Yamauchi, T ^b   Ootsuka, F ^c   Mitsuda, K ^a   Hase, M ^b   Nakamura, T ^b   Kawahara, T ^a   Onai, T ^a  

^a HITACHI LTD   (Japan)

^b HOSEI UNIVERSITY   (Japan)

^c Device Development Center   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CARRIER MOBILITY; DIELECTRIC MATERIALS; ELECTRIC CURRENT CONTROL; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; LEAKAGE CURRENTS; MASKS; NITROGEN OXIDES; SEMICONDUCTOR DEVICE STRUCTURES;

GATE INDUCED BARRIER LOWERING; OFFSET SOURCE DRAIN STRUCTURE; PHASE SHIFT MASKS; RADIO FREQUENCY APPLICATIONS; RESIST TRIMMING; SPIKE ANNEALING; SUPER STEEP CHANNEL; SYSTEM ON A CHIP;

CMOS INTEGRATED CIRCUITS;

EID: 0035714811     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2001.979472     Document Type: Article

References (2)

1. A 1000-MIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias
2. 1/f noise in CMOS transistors for analog applications