Modelling of multi-layered power supply planes with vias

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 69-72

  Lee, Shih Yen ^a   Yeo, Yong Kee ^a   Yeo, Mui Seng ^a   Iyer, Mahadevan K ^a   Do, Nhon ^a   Wong, Wui Weng ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC LOSSES; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTRONICS PACKAGING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; TRANSMISSION LINE THEORY;

MICROPROCESSOR PACKAGE; MULTILAYERED POWER SUPPLY; SIMULTANEOUS SWITCHING NOISE;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0035701570     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. High frequency modelling of power/ground plane pairs with lossy substrates
2. A comparative study of different plane modelling methodologies for high density electronic packages
3. High speed digital design
4. Modeling via hole grounds in microstrip
5. Computation and effect of field penetration through planes in multi-layered package power distribution networks for giga-processors