Test path simulation and characterisation

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 415-423

  Helmreich, Klaus ^a  

^a Advantest Test Eng Solutions GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; CONSTRAINT THEORY; CROSSTALK; DATA STORAGE EQUIPMENT; INTERFACES (MATERIALS); TIMING CIRCUITS;

DEVICE INTERFACES (DI);

INTEGRATED CIRCUIT TESTING;

EID: 0035687311     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Impedance measurement in time and frequency domain
2. Probing techniques for sigal performance measurements in high data rate testing
3. RF signal integrity characterisation of probe cards
4. International technology roadmap for semiconductors 1999 and 2000 update, test and test equipment
5. Design-for-test methods for stand-alone SRAMS at 1Gb/s/pin and beyond
6. Device interfacing: The weakest link in the chain to break into the giga bit domain ?
7. Productivity optimisation by quality proven test fixtures
8. Self test architecture for testing complex memory structures