Device interfacing: The weakest link in the chain to break into the giga bit domain?

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 995-1004

  Schoettmer, Ulrich ^a   Wagner, Chris ^b   Bleakley, Tom ^b  

^a AGILENT TECHNOLOGIES   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; INTERFACES (COMPUTER); MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

SECOND ORDER EFFECTS; SIGNAL DELIVERY PATH;

INPUT OUTPUT PROGRAMS;

EID: 0034479215     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2000.894312     Document Type: Article

References (3)

1. T. P. Warwick An accurate simulation model of the ATE test environment for very high speed devices Proceedings of the International Test Conference Proceedings of the International Test Conference 1999
2. Y. Cai Towards a standardized procedure for automated test equipment timing accuracy evaluation Proceedings of the International Test Conference Proceedings of the International Test Conference 1999
3. M. R. Barber Subnanosecond timing measurements of MOS devices using modern VLSI test systems Proceedings of the International Test Conference Proceedings of the International Test Conference 1983