Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 768-775

  Vollrath, Joerg ^a   Rooney, Randall ^a  

^a INFINEON TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; FAILURE ANALYSIS; HIGH TEMPERATURE TESTING; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR STORAGE;

BIT FAIL MAPS;

RANDOM ACCESS STORAGE;

EID: 0035684157     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966698     Document Type: Article

References (4)

1. Compressed bit fail maps for memory fail pattern classification
2. Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
3. Tutorial: SDRAM characterization