Computing embedded positive feedback loops in analog circuits using nullors

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2001, Pages 53-56

  Tlelo Cuautle, E ^a   Sarmiento Reyes, L A ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC ADMITTANCE; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; SEMICONDUCTOR DEVICE MODELS; TRANSCONDUCTANCE;

ADMITTANCE MATRIX; BIPOLAR JUNCTION TRANSISTORS; CONGRUENCE TRANSFORM; NULLORS; OPERATIONAL TRANSCONDUCTANCE AMPLIFIER; PARTITION-MATRIX-BASED METHOD; POSITIVE-FEEDBACK LOOPS;

ELECTRIC NETWORK ANALYSIS;

EID: 0035574877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A partition method in order to find embedded flip-flop structures in transistor circuits by applying graph theory concepts
2. Unified DC analysis for the four kinds of basic amplifiers
3. How to identify unstable dc operating points
4. Linear integrated networks: Fundamentals
5. Development of an efficient bias method within an environment of design automation for analog electronic circuits
6. Computer methods for circuit analysis and design
7. All two-transistor circuits possess at most three dc equilibrium points
8. Biasing analog circuits using the nullor concept