Partition method in order to find embedded flip-flop structures in transistor circuits by applying graph theory concepts

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1997, Pages 91-94

  Tlelo Cuautle, E ^a   Sarmiento Reyes, A ^a  

^a Instituto Tecnologico de Puebla   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; FEEDBACK; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS;

FEEDBACK ADMITTANCE; PARTITION METHOD;

FLIP FLOP CIRCUITS;

EID: 0031382892     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)