FPGA hardware implementation of an RNS FIR digital filter

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2001, Pages 1340-1344

  Kaluri, Kadambari ^a   Leong, Wen Fung ^a   Tan, Kah Howe ^a   Johnson, Louis ^a   Soderstrand, Michael ^a  

^a Oklahoma State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FIR FILTERS; NUMBER THEORY; RANDOM ACCESS STORAGE; TABLE LOOKUP;

CORE GENERATOR; RESIDUE NUMBER SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035573376     PISSN: 10586393     EISSN: None     Source Type: Journal    
DOI: 10.1109/ACSSC.2001.987709     Document Type: Article

References (12)

1. RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic
2. Pipelined Hogenauer CIC filters using field-programmable logic and residue number system
3. The design of residue number system arithmetic units for a VLSI adaptive equalizer
4. VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels
5. An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT
6. A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation
7. A high-speed residue-to-binary converter and a scheme for its VLSI implementation
8. Near-optimal residue to binary converter for the moduli
9. RNS-to-binary conversion for efficient VLSI implementation
10. An RNS to binary converter in a three moduli set with common factors
11. Transposed form FIR filters