Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Solid-State Electronics

Volumn 45, Issue 12, 2001, Pages 2077-2081

  Hanajiri, T ^a   Toyabe, T ^a   Sugano, T ^a  

^a TOYO UNIVERSITY   (Japan)

Author keywords

Full depletion; Full inversion; Partial depletion; SOI MOSFET

Indexed keywords

CHARGE CARRIERS; COMPUTER SIMULATION; ELECTRIC CONDUCTANCE; ELECTRIC CURRENTS; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0035545666     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(01)00131-9     Document Type: Article

References (11)

1. Investigations on high-temperature thermal oxidation process at top and bottom interfaces of top silicon of SIMOX wafers
2. Silicon on insulator material technology
3. Fabrication of 40-150 nm gate length ultrathin n-MOSFETs using ELTRAN SOI wafers
4. Subthreshold slope of thin-film SOI MOSFET's
5. Three-dimensional device simutators CADDETH with highly convergent matrix solution algorithms
6. Field-dependent mobility model for two-dimensional numerical analysis of MOSFETs
7. A mobility model for carriers in the MOS inversion layer
8. Quantum mechanical influences on short-channel effects in ultra-thin MOSFET/SIMOX devices
9. Features of ultimately miniaturized MOSFETs/SOI: A new stage in device physics and design concepts
10. VLSI limitations from drain-induced barrier lowering
11. A simple theory to predict the threshold voltage of short channel