-
1
-
-
0024629437
-
Two-dimensional simulation and measurement of high-performance MOSFFT's made on a very thin SOI film
-
M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, "Two-dimensional simulation and measurement of high-performance MOSFFT's made on a very thin SOI film," IEEE Trans. Electron Devices, vol. 36, pp. 493-503, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 493-503
-
-
Yoshimi, M.1
Hazama, H.2
Takahashi, M.3
Kambayashi, S.4
Wada, T.5
Kato, K.6
Tango, H.7
-
2
-
-
33746189368
-
0.1μm-Gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer
-
Ext. Abstract
-
Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, "0.1μm-Gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer," IEEE IEDM, Ext. Abstract, pp. 675-678, 1991.
-
(1991)
IEEE IEDM
, pp. 675-678
-
-
Omura, Y.1
Nakashima, S.2
Izumi, K.3
Ishii, T.4
-
3
-
-
0027886706
-
Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET's
-
Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET's," IEEE Electron Device Lett., vol. 14, pp. 569-571, 1993.
-
(1993)
IEEE Electron Device Lett.
, vol.14
, pp. 569-571
-
-
Omura, Y.1
Horiguchi, S.2
Tabe, M.3
Kishi, K.4
-
4
-
-
0347083676
-
One-dimensional conduction of ultra fine silicon quantum wires
-
Makuhari, Japan
-
K. Morimoto, Y. Hirai, K. Yuki, K. Inoue, M. Niwa, and J. Yasui, "One-dimensional conduction of ultra fine silicon quantum wires," Ext. Abst. 1993 Int. Conf. Solid-State Dev. Mat., Makuhari, Japan, 1993, pp. 344-346.
-
(1993)
Ext. Abst. 1993 Int. Conf. Solid-State Dev. Mat.
, pp. 344-346
-
-
Morimoto, K.1
Hirai, Y.2
Yuki, K.3
Inoue, K.4
Niwa, M.5
Yasui, J.6
-
5
-
-
0001780619
-
Quantized conductance of a si wire fabricated using SIMOX technology
-
Yokohama, Japan
-
Y. Nakajima, Y. Takahashi, S. Horiguchi, K. Iwadate, H. Namatsu, K. Kurihara, and M. Tabe, "Quantized conductance of a si wire fabricated using SIMOX technology," Ext. Abst. 1994 Int. Conf. Solid-State Dev. Mat., Yokohama, Japan, 1994, pp. 538-540.
-
(1994)
Ext. Abst. 1994 Int. Conf. Solid-State Dev. Mat.
, pp. 538-540
-
-
Nakajima, Y.1
Takahashi, Y.2
Horiguchi, S.3
Iwadate, K.4
Namatsu, H.5
Kurihara, K.6
Tabe, M.7
-
6
-
-
0018767303
-
Threshold and subthreshold characteristics theory for a very small burried-channel MOSFET using a majority-carrier distribution model
-
Y. Omura, and K. Ohwada, "Threshold and subthreshold characteristics theory for a very small burried-channel MOSFET using a majority-carrier distribution model," Solid-State Electron., vol. 22, pp.1045-1051, 1979.
-
(1979)
Solid-State Electron.
, vol.22
, pp. 1045-1051
-
-
Omura, Y.1
Ohwada, K.2
-
7
-
-
0020205487
-
A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator
-
Y. Omura, "A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator," IEEE Trans. Electron Devices. vol. ED-29, pp. 1749-1755, 1982.
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
, pp. 1749-1755
-
-
Omura, Y.1
-
8
-
-
0029252469
-
Low-temperature drain current characteristics in sub-10-nm-thick SOI nMOSFET's on SIMOX substrates
-
Y. Omura and M. Nagase, "Low-temperature drain current characteristics in sub-10-nm-thick SOI nMOSFET's on SIMOX substrates," Jpn. J. Appl. Phys., vol. 34, pp. 812-816, 1995.
-
(1995)
Jpn. J. Appl. Phys.
, vol.34
, pp. 812-816
-
-
Omura, Y.1
Nagase, M.2
-
9
-
-
6344290643
-
Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
-
T. Sekigawa and Y. Hayashi, "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate," Solid-State Electron, vol. 27, pp. 827-828, 1984.
-
(1984)
Solid-State Electron
, vol.27
, pp. 827-828
-
-
Sekigawa, T.1
Hayashi, Y.2
-
10
-
-
85056911965
-
Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?
-
Ext. Abstract
-
D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?," Ext. Abstract, IEEE 1992 IEDM, pp. 553-556, 1991.
-
(1991)
IEEE 1992 IEDM
, pp. 553-556
-
-
Frank, D.J.1
Laux, S.E.2
Fischetti, M.V.3
-
11
-
-
0037496574
-
Thickness increment of buried oxide in a SIMOX wafer by high-temperature oxidation
-
S. Nakashima, T. Katayama, Y. Miyamura, A. Matsuzaki, M. Imai, K. Izumi, and N. Ohwada, "Thickness increment of buried oxide in a SIMOX wafer by high-temperature oxidation," Proc. IEEE 1994 Int. SOI Conf., pp. 71-72, 1994.
-
(1994)
Proc. IEEE 1994 Int. SOI Conf.
, pp. 71-72
-
-
Nakashima, S.1
Katayama, T.2
Miyamura, Y.3
Matsuzaki, A.4
Imai, M.5
Izumi, K.6
Ohwada, N.7
-
12
-
-
0004734595
-
Two-dimensionally confined carrier injection phenomena in sub-10-nm-thick SOI insulated-gate pn-junction devices
-
Osaka, Japan
-
Y. Omura, "Two-dimensionally confined carrier injection phenomena in sub-10-nm-thick SOI insulated-gate pn-junction devices," Ext. Abst. Int. Conf., Solid State Devices and Mat., Osaka, Japan, 1995, pp. 563-565.
-
(1995)
Ext. Abst. Int. Conf., Solid State Devices and Mat.
, pp. 563-565
-
-
Omura, Y.1
-
13
-
-
4243159599
-
-
to be submitted
-
_, to be submitted.
-
-
-
|