An architecture and implementation of MPEG audio layer III decoder using dual-core DSP

IEEE Transactions on Consumer Electronics

Volumn 47, Issue 4, 2001, Pages 928-933

  Lee, Kyu Ha ^a   Lee, Keun Sup ^b   Hwang, Tae Hoon ^b   Park, Young Cheol ^b   Youn, Dae Hee ^b  

^a Samsung Thales   (South Korea)

^b Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUDIO SYSTEMS; CELLULAR TELEPHONE SYSTEMS; CONTROL SYSTEM ANALYSIS; COST EFFECTIVENESS; DATA COMPRESSION; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; FLASH MEMORY; PARALLEL PROCESSING SYSTEMS; USER INTERFACES;

AUDIO QUALITY; BUFFERING; DECODING ALGORITHM; FILE MANAGEMENT SYSTEM; MOVING PICTURE EXPERT GROUP;

DECODING;

EID: 0035520247     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.982810     Document Type: Article

References (8)

1. A fast MPEG-audio layer III algorithm for a 32-bit MCU
2. A low full accuracy MPEG1 audio layer III(MP3) decoder with on-chip data converters
3. A low-power MPEG audio III decoder IC with an intergrated digital-to-analog converter
4. A new algorithm to compute the discrete cosine transform